A FLEXIBLE PARALLEL ARCHITECTURE ADAPTED TO BLOCK-MATCHING MOTION-ESTIMATION ALGORITHMS

This paper describes a novel architecture that offers the flexibility of implementing widely varying motion-estimation algorithms. To achiev e real-time performance, we employ multiple processing elements (PE's) which communicate with multiple memory banks via a multistage interco nnection network. Three different block-matching algorithms-full searc h, three-step search, and conjugate-direction search-have been mapped onto this architecture to illustrate its programmability. We schedule the desired operations and design the required data-flow in such a way that processor utilization is high and memory bandwidth is at a feasi ble level. The details regarding the flow of the pixel data and the sc heduling and allocation of the desired ALU operations (which pixels ar e processed on which processors in which clock cycles) are described i n the paper, We analyze the performance of the proposed architecture f or several different interconnection networks and data-memory organiza tions.