VLSI DESIGN OF HIGH-SPEED TIME-RECURSIVE 2-D DCT IDCT PROCESSOR FOR VIDEO APPLICATIONS/

In this paper we present a full-custom VLSI design of high-speed 2-D D CT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been implemented to demonstrate its performance. We show that the VLSI implementation of this class of DCT /IDCT algorithms can easily meet the high-speed requirements of high-d efinition television (HDTV) due to its modularity, regularity, local c onnectivity, and scalability. Our design of the 8 x 8 DCT/IDCT can ope rate at 50 MHz (or have a 50 MSamples/s throughput) based on a very co nservative estimate under 1.2 mu CMOS technology. In comparison to the existing designs, our approach offers many advantages that can be fur ther explored for even higher performance.