DEVELOPMENT OF PROCESS FOR LOW ON-RESISTANCE VERTICAL POWER MOSFETS

Authors
KOBAYASHI K NINOMIYA Y TAKAHASHI M MARUOKA M
Citation
K. Kobayashi et al., DEVELOPMENT OF PROCESS FOR LOW ON-RESISTANCE VERTICAL POWER MOSFETS, NEC research & development, 35(4), 1994, pp. 433-437
Citations number
NO
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
NEC research & development → ACNP
ISSN journal
0547051X
Volume
35
Issue
4
Year of publication
1994
Pages
433 - 437
Database
ISI
SICI code
0547-051X(1994)35:4<433:DOPFLO>2.0.ZU;2-N
Abstract
A low on-resistance process for 60 V n-channel power MOSFET was develo ped. A.R(on) (Q.mm(2)) was reduced by 45% compared with the convention al one by downsizing the unit cell and employing the arsenic-doped low resistivity substrate. Also, the parasitic capacitance was reduced, a nd the switching time was improved by approximately 30%.