VOLTAGE-MODE CMOS QUATERNARY LATCH CIRCUIT

A new voltage-mode CMOS quaternary threshold logic latch circuit that has been realised in a standard 2 mum p-well polysilicongate CMOS tech nology is presented. This circuit requantises quaternary logical volta ges during a SETUP clock mode and latches the input value during the H OLD clock mode. Using a 5V supply and logical voltage increments of 1. 67V, the quaternary latch has a worst-case total SETUP and HOLD time o f approximately 5.7 ns, and best single-level transition total SETUP a nd HOLD time of approximately 0.9ns.