PARALLEL LOGIC SIMULATION OF VLSI SYSTEMS

Fast, efficient logic simulators are an essential tool in modern VLSI system design. Logic simulation is used extensively for design verific ation prior to fabrication, and as VLSI systems grow in size, the exec ution time required by simulation is becoming more and more significan t. Faster logic simulators will have an appreciable economic impact, s peeding time to market while ensuring more thorough system design test ing. One approach to this problem is to utilize parallel processing, t aking advantage of the concurrency available in the VLSI system to acc elerate the logic simulation task. Parallel logic simulation has recei ved a great deal of attention over the past several years, but this wo rk has not yet resulted in effective, high-performance simulators bein g available to VLSI designers. A number of techniques have been develo ped to investigate performance issues: formal models, performance mode ling, empirical studies, and prototype implementations. Analyzing repo rted results of these techniques, we conclude that five major factors effect performance: synchronization algorithm, circuit structure, timi ng granularity, target architecture, and partitioning. After reviewing techniques for parallel simulation, we consider each of these factors using results reported in the literature. Finally we synthesize the r esults and present directions for future research in the field.