TRAP-DRIVEN SIMULATION WITH TAPEWORM-II

Citation
R. Uhlig et al., TRAP-DRIVEN SIMULATION WITH TAPEWORM-II, ACM SIGPLAN NOTICES, 29(11), 1994, pp. 132-144
Citations number
45
Categorie Soggetti
Computer Sciences","Computer Science Software Graphycs Programming
Journal title
Volume
29
Issue
11
Year of publication
1994
Pages
132 - 144
Database
ISI
SICI code
Abstract
Tapeworm II is a software-based simulation tool that evaluates the cac he and TLB performance of multiple-task and operating system intensive workloads. Tapeworm resides in an OS kernel and causes a host machine s's hardware to drive simulations with kernel traps instead of with ad dress traces, as is conventionally done. This allows Tapeworm to quick ly and accurately capture complete memory referencing behavior with a limited degradation in overall system performance. This paper compares trap-driven simulation, as implemented in Tapeworm, with the more com mon technique of trace-driven memory simulation with respect to speed accuracy, portability and flexibility. Results: For reasonable miss ra tios, Tapeworm simulations are significantly faster than traditional t race-driven simulations. Tapeworm typically slows a system down by les s than an order of magnitude (10x) when cache miss rations are under 1 0%, and slowdowns approach zero as miss ratios decrease. Tapeworm can employ set sampling techniques to further reduce slowdowns, but at the expense of higher measurement variance. Unlike trace-driven simulatio ns, which typically produce identical results from run to run, trap-dr iven simulations exhibit greater sensitivity to inherent variations in memory system behavior on a real machine. Less than 5% of Tapeworm's code is machine-dependent, enhancing its portability to different mach ines provided that they support a few essential primitive operations. Although the trap-driven approach is flexible enough to simulate most TLB and cache configurations, other architectural structures, such as write buffers or instruction pipelines cannot be simulated with this a pproach. Tapeworm implementations currently exist for TLB and instruct ion cache simulation on MIPS-based DECstations and for TLB simulation on a 486-based Gateway PC.