SURPASSING THE TLB PERFORMANCE OF SUPERPAGES WITH LESS OPERATING SYSTEM SUPPORT

Many commercial microprocessor architectures have added translation lo okaside buffer (TLB) support for superpages. Superpages differ from se gments because their size must be a power of two multiple of the base page size and they must be aligned in both virtual and physical addres s spaces. Very large superpages (e.g., 1MB) are clearly useful for map ping special structures, such as kernel data or frame buffers. This pa per considers the architectural and operating system support required to exploit medium-sized superpages (e.g., 64kB, i.e., sixteen times a 4KB base page size). First, we show that superpages improve TLB perfor mance only after invasive operating system modifications that introduc e considerable overhead. We then propose two subblock TLB designs as a lternate ways to improve TLB performance. Analogous to a subblock cach e, a complete-subblock TLB associates a tag with a superpage-sized reg ion but has valid bits, physical page number, attributes, etc., for ea ch possible base page mapping. A partial-subblock TLB entry is much sm aller than a complete-subblock TLB entry, because it shares physical p age number and attribute fields across base page mappings. A drawback of a partial-subblock TLB is that base page mappings can share a TLB e ntry only if they map to consecutive physical pages and have the same attributes. We propose a physical memory allocation algorithm, page re servation, that makes this sharing more likely. When page reservation is used, experimental results show partial-subblock TLBs perform bette r than superpage TLBs, while requiring simpler operating system change s. If operating system changes are inappropriate, however, complete-su bblock TLBs perform best.