THE PERFORMANCE ADVANTAGES OF INTEGRATING BLOCK DATA TRANSFER IN CACHE-COHERENT MULTIPROCESSORS

Integrating support for block data transfer has become an important em phasis in recent cache-coherent shared address space multiprocessors. This paper examines the potential performance benefits of adding this support. A set of ambitious hardware mechanisms is used to study perfo rmance gains in five important scientific computations that appear to be good candidates for using block transfer. Our conclusion is that th e benefits of block transfer are not substantial for hardware cache-co herent multiprocessors. The main reasons for this are (i) the relative ly modest fraction of time applications spend in communication amenabl e to block transfer, (ii) the difficulty of finding enough independent computation to overlap with the communication latency that remains af ter block transfer, and (iii) long cache lines often capture many of t he benefits of block transfer in efficient cache-coherent machines. In the cases where block transfer improves performance, prefetching can often provide comparable, if not superior, performance benefits. We al so examine the impact of varying important communication parameters an d processor speed on the effectiveness of block transfer, and comment on useful features that a block transfer facility should support for r eal applications.