A 2.2-W, 80-MHZ SUPERSCALAR RISC MICROPROCESSOR

A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described [1]. This 32-b implementation of the PowerPC(TM) architectur e is fabricated in a 3.3 V, 0.5 mu m, 4-level metal CMOS technology, r esulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performa nce 32/64-b system bus and separate execution units (boat, integer, lo ad store, and system units) result in peak instruction rates of three instructions per Clock cycle. Low-power design techniques are used thr oughout the entire design, including dynamically powered down executio n units. Typical power dissipation is kept under 2.2 W at 80 MHz. Thre e distinct levels of software-programmable, static, low-power operatio n-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to Bus clock ratios of 1x, 2x, 3x , and 4x are implemented to allow control of system power while mainta ining processor performance. As a result, workstation-level performanc e is packed into a low-power, low-cost design ideal for notebooks and desktop computers.