A 500-MHZ, 32-BIT, 0.4-MU-M CMOS RISC PROCESSOR

A 500 MHz, 32 bit RISC microprocessor has been experimentally develope d using an 8-stage pipelined architecture and high-speed circuits, inc luding a 500 MHz 1 kilobyte double-stage pipelined cache, a 1.8 ns reg ister file, a double-stage binary look-ahead carry (BLC) adder circuit , and a 500 MHz phase locked loop (PLL) frequency multiplier. Newly de veloped circuit-integrating techniques include a stacked power-line st ructure, which serves as a noise shield and also provides low bounce, a low voltage-swing interface circuit with on-chip adjustable terminat ion resistors, a small-skew clock distribution method, and a clock syn chronization circuit which provides small-skew clock among LSI chips. About 200 000 transistors are integrated into a 7.90 mm x 8.84 mm die area with 0.4 mu m CMOS fabrication technology, Power dissipation is 6 W at a 500 MHz operation and 3.3 V supply voltage,