A COMPACT POWER-EFFICIENT 3-V CMOS RAIL-TO-RAIL INPUT OUTPUT OPERATIONAL-AMPLIFIER FOR VLSI CELL LIBRARIES/

This paper presents a two-stage, compact, power-efficient 3 V CMOS ope rational amplifier with rail-to-rail input and output ranges. Because of its small die area of 0.04 mm(2), it is very suitable as a VLSI lib rary cell. The floating class-AB control is shifted into the summing c ircuit, which results in a noise and offset of the amplifier which are comparable to that of a three stage amplifier. A floating current sou rce biases the combined summing circuit and the class-AB control. This current source has the same structure as the class-AB control which p rovides a power-supply-independent quiescent current. Using the compac t architecture, a 2.6 MHz amplifier with Miller compensation and a 6.4 MHz amplifier with cascoded-Miller compensation has been realized. Th e opamps have, respectively, a bandwidth-to-supply-power ratio of 4 MH z/mW and 11 MHz/mW for a capacitive load of 10 pF.