A 6-GHZ 60-MW BICMOS PHASE-LOCKED LOOP

The design of a 6 GHz fully monolithic phase-locked loop fabricated in a 1 mu m, 20 GHz BiCMOS technology is described, The circuit incorpor ates a voltage-controlled oscillator that senses and combines the tran sitions in a ring oscillator to achieve a period equal to two ECL gate delays, A mixer topology is also used that exhibits full symmetry wit h respect to its inputs and operates with supply voltages as low as 1. 5 V, Dissipating 60 mW from a 2 V supply, the circuit has a tracking r ange of 300 MHz, an rms jitter of 3.1 ps, and phase noise of -75 dBc/H z at 1 kHz offset.