ELECTRICAL-PROPERTIES OF THE P(-GATE ELECTRODE OF AN A-SI())POLY-SI DOUBLE-LAYER/

The single and mixed p(+)-gate electrodes of a-Si and poly-Si layers w ere fabricated and analyzed by cross-sectional transmission electron m icroscopy, Raman, X-ray diffraction, secondary ion mass spectrometry a nd electrical measurements. The as-deposited a-Si layer, which transfo rmed to a large grain polycrystalline structure during annealing, show ed lower resistivity and less gate electrode-induced strain than the s ingle poly-Si layer. The interface in the mixed layer of a-Si and poly -Si layers showed a discontinuity of grains of upper and lower layers. The mixed electrode layers on 80 Angstrom, thick N2O oxide were impla nted with BF2+ at 30 keV and annealed at 900 degrees C to fabricate p( +)-gate MIS capacitors. The high frequency and quasi-static C-V measur ements of the MIS capacitors showed the formation of a shallow pi(+)-n junction in the Si substrate of MIS capacitors, caused by B and F ato ms penetrating into the Si substrate through the ultrathin N2O gate ox ide during annealing. However, the mixed layer including the a-Si laye r partially restricted B penetration into the Si substrate during furn ace annealing, and thus MIS capacitors with the mixed layer had better electrical properties, such as time dependent dielectric breakdown an d charge trapping, than those with the single poly-Si electrode struct ure. This might be due to less B penetration into the oxide layer and relaxation of residual stress in gate electrodes owing to phase transf ormation of a-Si to poly-Si.