VLSI ARCHITECTURE FOR THE WINOGRAD FOURIER-TRANSFORM ALGORITHM

A simple systolic architecture for the computation of the DFT using th e Winograd Fourier Transform algorithm is presented. The architecture is shown to be problem-size independent and to satisfy the limited ban dwidth constraint. By satisfying the above constraints, it is then sho wn to be naturally scalable within the limits allowed by the Winograd algorithm. The proposed architecture is compared with existing VLSI so lutions using Winograd's technique. Lastly, the feasibility of derivin g and using Winograd type algorithms for larger primes and prime-power s is studied.