A HALF-PEL PRECISION MOTION ESTIMATION PROCESSOR FOR NTSC-RESOLUTION VIDEO

The hybrid coding with motion compensated prediction and discrete cosi ne transform (MC+DCT) has been recognized as the standard technique in motion picture coding. In this paper, a motion estimation processor c ompatible with ITU-T H.261 and MPEG standards is described. A half-pel precision processing unit is introduced with an exhaustive block matc hing unit for integer-pel precision search. The necessary processing p ower for the exhaustive block matching is implemented with a 1-dimensi onal array structure utilizing a subsampling technique. In comparison with the conventional 2-dimensional array structure, path of the data transfer is so simple that the low power dissipation characteristic is obtained. The problem of communication bandwidth to the frame memory, which is a bottleneck of half-pel precision motion estimation, is sol ved by introducing a candidate pixel buffer into the interprocessor da ta transfer. A static latch circuit with conflict free operation is ne wly developed for reducing the power consumption. This chip is capable of processing NTSC-resolution Video in real-time at the 40 MHz operat ion. The chip integrates about 540 k transistors in the 121 mm(2) die using 0.8 mu m double metal CMOS technology.