A PLL-BASED PROGRAMMABLE CLOCK GENERATOR WITH 50-MHZ TO 350-MHZ OSCILLATING RANGE FOR VIDEO SIGNAL PROCESSORS

A programmable clock generator, based on a phase-locked loop (PLL) cir cuit, has been developed with 0.5-mu m CMOS triple-layer Al interconne ction technology for use as an on-chip clock generator in a 300-MHz vi deo signal processor. The PLL-based clock generator generates a clock signal whose frequency ranges from 50 to 350 MHz which is an integral multiple, from 2 to 16, of an external dock frequency. In order to ach ieve stable operation within this wide range, a voltage controlled osc illator (VCO) with selectable low VCO gain characteristics has been de veloped. Experimental results show that the clock generator generates a 297-MHz clock with a 27-MHz external clock, with jitter of 180 ps an d power dissipation of 120 mW at 3.3-V power supply, and it can also o scillate up to 348 MHz with a 31.7-MHz external clock.