A FLOORPLANNING METHOD WITH TOPOLOGICAL CONSTRAINT MANIPULATION IN VLSI BUILDING-BLOCK LAYOUT

This paper presents a heuristic floorplanning method that improves the method proposed by Vijayan and Tsay [7],[8]. It is based on tentative insertion of constraints, that intentionally produces redundant const raints to make it possible to search in a wide range of solution space . The proposed method can reduce the total area of blocks with the rem oval and insertion of constraints on the critical path in both horizon tal and vertical constraint graphs. Experimental results for MCNC benc hmarks showed that the quality of solutions of the proposed method is better than [7],[8] by about 15% on average, and even for the large nu mber of blocks, the proposed method keeps the high quality of solution s.