A GLOBAL ROUTER OPTIMIZING TIMING AND AREA FOR HIGH-SPEED BIPOLAR LSIS

A timing-driven global routing algorithm is proposed that directly mod els the path-based timing constraints. By keeping track of the critica l path delay and channel densities, and using novel heuristic criteria , it can select routing paths that minimize area as well as satisfy th e timing constraints. Using bipolar-specific features, this router can be used to design LSI chips that handle signals with speeds greater t hat a gigabit per second. Experimental results shows an average delay improvement of 17.6%.