3-DIMENSIONAL SIMULATION OF CHARGE COLLECTION AND MULTIPLE-BIT UPSET IN SI DEVICES

In this paper, three-dimensional numerical simulation is used to explo re the basic charge-collection mechanisms in silicon n(+)/p diodes. Fo r diodes on lightly-doped substrates (<1x10(15) cm(-3)) struck by a 10 0-MeV Fe ion, the funneling effect is very strong and essentially all collection is by funnel-assisted drift. This drift collection may occu r as late as several nanoseconds after the strike, later than is usual ly associated with drift collection. For moderately doped substrates ( =1x10(16) cm(-3)) and epitaxial structures grown on heavily-doped subs trates, the funnel effect is weaker and drift and diffusion are of mor e equal importance. For 5-MeV He (alpha-particle) strikes with low-den sity charge tracks, the charge-collection transient exhibits both drif t and diffusion regimes regardless of the substrate doping. Simulation s of diodes with passive external loads indicate that while the curren t response is altered considerably by the load, total collected charge is not greatly affected for the simple resistive loads studied. Three -dimensional mixed-mode simulation is performed to investigate charge- collection behavior and upset mechanisms in complete CMOS SRAM cells. Simulations of double SRAM cell structures indicate that only collecti on by diffusion from ''between-node'' strikes is capable of producing multiple-bit upsets in the simulated technology. Limitations of the si mulations, specifically carrier-carrier scattering models and large co ncentration gradients, are also discussed.