SINGLE-EVENT GATE RUPTURE IN VERTICAL POWER MOSFETS - AN ORIGINAL EMPIRICAL EXPRESSION

For the first time, an empirical expression is derived that describes the susceptibility of a power double-diffused metal-oxide semiconducto r (DMOS) field-effect transistor (FET) to single-event gate rupture (S EGR) induced by the interaction of mono-energetic ions with regions of the n-epi, gate oxide, and polysilicon gate. Using this expression, t he failure threshold voltages for the gate and drain can be analytical ly determined for any particular value of energy deposition along the ion's path or more commonly described as the ion's linear energy trans fer (LET) function. This paper delineates our research, an in-depth st udy of vertical power DMOS transistors, having a 50-nm gate oxide and a strong SEGR response, subjected to various monoenergetic ions, repre senting particular values of LET between 0 and 83 MeV.cm(2) mg(-1). A description of the devices characterized, the test setup and test meth odology employed, the failure threshold voltages measured, and the ana lysis techniques used are all summarized. Finally, an empirical equati on is presented that portrays the locus of SEGR in the {-V-GS, V-DS} p lane for all values of LET.