2 CMOS MEMORY CELLS SUITABLE FOR THE DESIGN OF SEU-TOLERANT VLSI CIRCUITS

Authors
VELAZCO R BESSOT D DUZELLIER S ECOFFET R KOGA R
Citation
R. Velazco et al., 2 CMOS MEMORY CELLS SUITABLE FOR THE DESIGN OF SEU-TOLERANT VLSI CIRCUITS, IEEE transactions on nuclear science, 41(6), 1994, pp. 2229-2234
Citations number
9
Categorie Soggetti
Nuclear Sciences & Tecnology","Engineering, Eletrical & Electronic
Journal title
IEEE transactions on nuclear science → ACNP
ISSN journal
00189499
Volume
41
Issue
6
Year of publication
1994
Part
1
Pages
2229 - 2234
Database
ISI
SICI code
0018-9499(1994)41:6<2229:2CMCSF>2.0.ZU;2-V
Abstract
Two new CMOS memory cells, called HIT cells, designed to be SEU-immune are presented. Compared to previously reported design hardened soluti ons, the HIT cells feature better electrical performances and consume less silicon area. SEU tests performed on a prototype chip prove the e fficiency of the approach.