Single Event Upset (SEU) characteristics of a digital emitter coupled
logic (ECL) device clocking at 0:5, 1, and 3.2 GHz and at temperatures
of 5, 75, and 105 degrees C are presented. The test technique is expl
ained. Observations of two types of upsets, phase upsets at low Linear
Energy Transfer (LETs) and amplitude upsets at high LETs are also pre
sented. The cause of phase upsets is discussed: The effect of each typ
e of upset on the system is discussed. The upset cross section and LET
threshold seem to be insensitive to temperatures below 75 degrees C a
nd to the clock frequencies tested.