In this paper we present the effect of total dose ionization of nonhar
dened field programmable gate arrays considered for space applications
. By irradiating test structures and modeling the circuits that includ
e total dose degradation, the basic leakage mechanism in the design at
elevated temperature can be understood. Results show that a large arr
ay of CMOS inverter structures will conduct large currents when the th
reshold voltages of the p and n-channel transistors reach the transiti
on point of switching. Results show that if the n- and p-channel thres
holds were to be increased in the process, this problem can be mitigat
ed and hardness above 100 krad(Si) can be achieved.