EFFECTS OF BURN-IN ON RADIATION HARDNESS

Transistors and ICs were irradiated with or without pre-irradiation el evated-temperature biased stresses (i.e., burn-in). These stresses lea d to larger radiation-induced transistor threshold-voltage shifts and increases in IC static power supply leakage current (two orders of; ma gnitude) in stressed ICs than for ICs not subjected to a stress. In ad dition, these stresses led to reduced degradation in timing parameters . The major cause of the differences is less radiation-induced interfa ce-trap buildup for transistors subjected to an elevated-temperature b iased stress. These results were observed for two distinctly different technologies and have significant implications on hardness assurance testing. One could significantly (1) overestimate degradation in timin g parameters resulting in the rejection of acceptable ICs and increase d system cost, or (2) underestimate the increase in static supply leak age current of ICs leading to system failure. These results suggest th at radiation qualification testing must be performed on integrated cir cuits that have been subjected to all high-temperature biased stresses experienced in normal production flow or system use.