BITONIC SORTING USING AN OPTOELECTRONIC RECIRCULATING ARCHITECTURE

An optoelectronic bitonic sorter based on a recirculating architecture is presented. The data are input in word parallel-bit parallel fashio n and processed by two smart pixel arrays made up of bitwise compare-a nd-exchange modules. Along with the logic design, the control and sync hronization of the bitwise compare-and-exchange modules are discussed. Finally, the capacity, hardware requirements, response time, and thro ughput of the recirculating bitonic sorter are compared with a pipelin e implementation. The proposed recirculating architecture is shown to require less hardware than the pipelined systems. However, the decreas e in hardware results in a decrease in system throughput.