The timing jitter induced by pointer adjustments in the basic STM-1 fr
ame represents a serious technical problem in SDH-based networks. This
paper describes two jitter reduction techniques to cope with this phe
nomenon. The first technique is based on digital phase-lock loop (PLL)
theory, and obtained through two structural modifications of a previo
usly proposed desynchronizer. The second technique is entirely novel,
and it avoids the generation of the random noise with uniform probabil
ity density, which is required in PLL-type desynchronizers to smooth t
he 1-b phase steps at the output of the first stage. We describe two d
ifferent methods to adapt the speed of this desynchronizer to the inco
ming pointer adjustment statistics. The performance of both jitter red
uction techniques is investigated in both the normal mode and the degr
aded mode of operation of the network, Using a design example, it is s
hown that the peak-to-peak jitter in the presence of isolated pointer
adjustments that characterize the normal operation mode is kept below
0.1 b. It is also shown that with frequency offsets up to 4.6 ppm in t
he degraded mode, the peak-to-peak jitter does not exceed 0.6 b. Lower
jitter values are achievable if the complexity and memory requirement
s of the desynchronizer are allowed to increase.