DELAY-FAULT COVERAGE, TEST SET SIZE, AND PERFORMANCE TRADE-OFFS

The main disadvantage of the path delay fault model is that to achieve 100% testability every path must be tested. Since the number of paths is usually exponential in circuit size, this implies very large test sets for most circuits. Not surprisingly, all known analysis and synth esis techniques for 100% path delay fault testability are computationa lly infeasible on large circuits. We prove that 100% delay fault testa bility is not necessary to guarantee the speed of a combinational circ uit. There exist path delay faults which can never impact the circuit delay (computed using any correct timing analysis method) unless some other path delay faults also affect it. These are termed robust depend ent delay faults and need not be considered in delay fault testing. Ne cessary and sufficient conditions under which a set of path delay faul ts is robust dependent are proved; this yields more accurate and incre ased delay fault coverage estimates than previously used. Next, assumi ng only the existence of robust delay fault tests for a very small set of paths, we show how the circuit speed (clock period) can be selecte d such that 100% robust delay fault coverage is achieved. This leads t o a quantitative tradeoff between the, testing effort (measured by the size of the test set) for a circuit and the verifiability of its perf ormance. Finally, under a bounded delay model, we show that the test s et size can be reduced while maintaining the delay fault coverage for the specified circuit speed. Examples and experimental results are giv en to shelf the effect of these three techniques on the amount of dela y fault testing necessary to guarantee correct operation.