HIGH-SPEED VLSI ARCHITECTURES FOR SOFT-OUTPUT VITERBI DECODING

During the last years decoding algorithms that make not only use of so ft quantized inputs but also deliver soft decision outputs have attrac ted considerable attention because additional coding gains are obtaina ble in concatenated systems. A prominent member of this class of algor ithms is the Soft-Output Viterbi Algorithm. In this paper two architec tures for high speed VLSI implementations of the Soft-Output Viterbi-A lgorithm are proposed and area estimates are given for both architectu res. The well known trade-off between computational complexity and sto rage requirements is played to obtain new VLSI architectures with incr eased implementation efficiency. Area savings of up to 40% in comparis on to straightforward solutions are reported.