EFFICIENT DIGITAL-TECHNIQUES FOR IMPLEMENTING A CLASS OF FAST PHASE-LOCKED LOOPS (PLLS)

Circuit configurations making use of counters are described to efficie ntly implement controllers for time-optimal and finite-time responses in phase-locked loops (PLL's), The new PLL's, solving the responsivene ss problem with conventional PLL's, require quite complicated operatio ns, including adders and subtracters, The proposed schemes taking adva ntage of normal and loadable operations of counters for these operatio ns provide for gate count saving of about 30%.