We investigated the electrical properties of porous silicon layers pre
pared on one side of a silicon single-crystal wafer and sandwiched wit
h it between two 25 nm thick Au films. When a sum of a constant bias v
oltage and a voltage pulse are applied over this structure it behaves
like a capacitor, with the capacitance decreasing with increasing bias
voltage, This phenomenon is attributed to interface defects between t
he Au film and porous silicon. characterized by a Schottky barrier hei
ght of 1.2 eV.