VLSI ARCHITECTURES FOR VIDEO COMPRESSION - A SURVEY

The paper presents an overview on architectures for VLSI implementatio ns of video compression schemes as specified by standardization commit tees of the ITU and ISO. VLSI implementation strategies are discussed and split into function specific and programmable architectures. As ex amples for the function oriented approach, alternative architectures f or DCT and block matching will be evaluated. Also dedicated decoder ch ips are included. Programmable video signal processors are classified and specified as homogeneous and heterogenous processor architectures. Architectures are presented for reported design examples from the lit erature. Heterogenous processors outperform homogeneous processors bec ause of adaptation to the requirements of special subtasks by dedicate d modules. The majority of heterogeneous processors incorporate dedica ted modules for high performance subtasks of high regularity as DCT an d block matching. By normalization to a fictive 1.0 mum CMOS process t ypical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This rela tionship indicates a figure of merit for silicon efficiency.