CMOS HIGH-SPEED DUAL-MODULUS FREQUENCY-DIVIDER FOR RF FREQUENCY-SYNTHESIS

The architecture of a high-speed low-power-consumption CMOS dual-modul us frequency divider is presented. Compared to other designs fabricate d with comparable CMOS technologies, this architecture has a better po tential for high-speed operation. The circuit consumes less power than previously reported CMOS circuits, and it approaches the performance previously achieved only by bipolar or GaAS devices. The proposed circ uit uses level-triggered differential logic to create an input-frequen cy-entrained oscillator performing a dual-modulus frequency division. In addition to high-speed and low-power consumption, the divider has a low-input signal level requirement which facilitates its incorporatio n into RF applications. Fabricated with a 1.2-mum 5-V CMOS technology, the divider operates up to 1.5 GHz, consuming 13.15 mW, and requiring less than 100 mV rms input amplitude.