DESIGN OF HIGH-SPEED, LOW-POWER FREQUENCY-DIVIDERS AND PHASE-LOCKED LOOPS IN DEEP-SUBMICRON CMOS

Deep submicron CMOS technologies offer the high speed and low power di ssipation required in multigigahertz communication systems such as opt ical data links and wireless products. This paper introduces the desig n of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 mum CMOS techn ology. Configured as a master-slave circuit, the divider achieves a ma ximum speed of 13.4 GHz with a power dissipation of 28 mW. The phase-l ocked loop employs a current-controlled oscillator and a symmetric mix er to operate at 3 GHz with a tracking range of +/-320 MHz, an rms jit ter of 2.5 ps, and a phase noise of -100 dBc/Hz while dissipating 25 m W.