This paper introduces a biasing scheme that overcomes the inherent dra
wbacks associated with high input common-mode range (CMR) amplifiers:
nonconstant transconductance (G(m)) and very poor common-mode rejectio
n ratio (CMRR). The proposed circuit achieves a constant amplifier G(m
) by maintaining a constant sum of the square-roots of the bias curren
ts of the complementary input pairs, while the high rejection to input
common-mode signals is achieved by making a gradual transition betwee
n these currents as function of the input common-mode component (V(in,
cm)). Experimental results obtained from a CMOS n-well 2 mum chip prot
otype with 5 V of total supply voltage, show a maximum transconductanc
e deviation less than 5% from its value for a common-mode input voltag
e at midsupply, as well as a CMRR improvement of 12 dB with respect to
the classical biasing scheme. Other representative figures of its exp
erimental behavior are also given.