TIMING OPTIMIZATION BY GATE RESIZING AND CRITICAL PATH IDENTIFICATION

Due to the rapid progress in VLSI technology, the overall complexity o f the chip has increased dramatically. There is a simultaneous need fo r more functions and higher speed in modern VLSI engineering. Therefor e, use of a minimum amount of extra hardware to meet timing requiremen ts is becoming a major issue in VLSI design. Here, we propose an effic ient method for timing optimization using gate resizing. To control th e hardware overhead, a minimum (or as small as possible) number of gat es are selected for resizing with the aid of a powerful benefit functi on. To guarantee the performance of timing optimization, a modified ve rsion of PODEM [1], called tau PODEM, ensures that each resized gate i s located on at least one critical path. Thus, resizing a gate definit ely reduces circuit delay. Simulation results demonstrate that our tim ing optimization method can efficiently reduce circuit delay with a li mited amount of gate resizing.