ON CORRECTION OF MULTIPLE DESIGN ERRORS

We consider the problem of correcting multiple design errors in combin ational circuits and in finite-state machines. The correction method i ntroduced for combinational circuits uses a single error correction sc heme iteratively to correct multiple errors. It uses a heuristic measu re that guides the selection of single, local circuit modifications th at reduce the distance between the incorrect implementation and the sp ecification. The distance is measured by the size of a correction hard ware. which is a block of logic that can be added to the implementatio n in order to correct it without performing additional circuit modific ations. The correction method for finite-state machines is based on th e use of pairwise distinguishing sequences for specification and imple mentation states, and employs the same hardware correction scheme. Exp erimental results are presented to support the effectiveness of the pr oposed methods.