BANDWIDTH OPTIMIZATION OF A LOW-POWER, HIGH-SPEED CMOS CURRENT OP AMP

A current op amp with a differential output and a single-ended input c an be configured from a single second generation current conveyor and an output stage with a differential floating current source. Owing to a very simple basic configuration with a single dominant pole, this de sign combines a high bandwidth with a high open loop gain. In this pap er we present the basic configuration, derive the fundamental equation s for the performance of the op amp, and describe some design consider ations with respect to an optimization of the op amp for a high bandwi dth. Simulation results are given from a commercially available 2 mu m CMOS process resulting in an open loop differential gain of 94dB and a gain-bandwidth product of 128MHz at a supply voltage of 3V and a sup ply current of 25 mu A. The design has been experimentally verified th rough a test circuit and experimental results from this confirm the ex pected behaviour.