AN AUTOMATON MODEL FOR SCHEDULING CONSTRAINTS IN SYNCHRONOUS MACHINES

We present a finite-state model for scheduling constraints in digital system design. We define a two-level hierarchy of finite-state machine s: a behavior FSM's input and output events are partially ordered in t ime; a register-transfer FSM is a traditional FSM whose inputs and out puts are totally ordered in time. Explicit modeling of scheduling cons traints is useful for both high-level synthesis and verification-we ca n explicitly search the space of register-transfer FSM's which impleme nt a desired schedule. State based models for scheduling are particula rly important in the design df control-dominated systems. This paper d escribes the BFSM model, describes several important operations and al gorithms on BFSM's and networks of communicating BPSM's, and illustrat es the use of BFSM's in high-level synthesis.