REDUCING ITERATION TIME WHEN RESULT DIGIT IS ZERO FOR RADIX-2 SRT DIVISION AND SQUARE-ROOT WITH REDUNDANT REMAINDERS - COMMENT

In a previous paper by P. Montuschi and L. Ciminiera, an architecture for shared radix 2 division and square root, has been presented whose main characteristic is the ability to avoid any addition/subtraction, when the digit 0 has been selected. Here, we emphasize the characteris tics of the digit selection mechanism used by Montuschi and Ciminiera by presenting a small modification of the digit selection hardware, wh ich has the benefit to further reduce the computation delay with respe ct to the time estimated in that work.