A FLOATING-POINT SYSTOLIC ARRAY-PROCESSING ELEMENT WITH SERIAL COMMUNICATION AND BUILT-IN SELF-TEST

This paper describes the design of a processing element (PE) for systo lic array applications. The PE, which can be configured as a multiplie r-accumulator or an inner product step processor, supports several of the most common systolic algorithms in signal processing and matrix ar ithmetic. Communication with neighbouring PEs is achieved through 18 o n-chip serial links, each operating at 50 Mbits per second. The device incorporates both scan path and built-in self-test features. Integrat ion of test circuitry with the serial communication ports permitted th e testability features to be implemented with a total area overhead of under 9%. The 30 k transistor ASIC device is implemented in 2 micron HCMOS gate array technology, packaged in a 48 pin DIP and performs at 10 MFLOPS.