A CHIP SET FOR PIPELINE AND PARALLEL PIPELINE FFT ARCHITECTURES

A chip set for pipelined and parallel pipelined FFT applications is pr esented. The set consists of two cascadeable chips with built-in self- test and a chip-interconnectivity test feature. The two ASICs are a 15 k gate Complex-Butterfly and a 9k gate FFT Switch. The Complex-Butterf ly uses redundant binary arithmetic (RBA), a modified Booth algorithm and a Wallace tree architecture to achieve a throughput of better than 25 Msamples/sec. The cascadeable FFT Switch is designed to support th e implementation of radix-2, 2N point, pipeline FFTs. Both devices hav e been fabricated in 1.5 mum CMOS gate array technology.