A FAST VLSI SYSTOLIC ARRAY FOR LARGE MODULUS RESIDUE ADDITION

The Residue number system (RNS) is inherently suited to high speed com putations using custom tailored VLSI systems. In this paper, an algori thm for residue addition, based on a novel, 'non unique' number repres entation scheme, is implemented by a systolic array embedded in a VLSI chip. The pipelined cells are implemented, using a true single phase clock dynamic circuit structure, with computer synthesized minimized t rees (switching trees). The array may be easily programmed by the user to accept any arbitrary modulus. Important applications of this array are in residue decoding and fault tolerant computation requring the u se of the Chinese Remainder Theorem where the modulus for addition is relatively large.