INTERCONNECT METALLIZATION FOR FUTURE DEVICE GENERATIONS

Advanced semiconductor device interconnects are on the brink of a dram atic change, With ever-increasing demand for faster logic devices and higher capacity memories, semiconductor designers will maintain the cu rrent trend toward shrinking design ground rules and increased interco nnect packing densities. As interconnect lines shrink and move closer together, the resistance of aluminum/ copper and tungsten conductors a nd the capacitance of structures with SiO2-based dielectrics limit fur ther increases in clock speed, Already, interconnect RC delays approxi mately equal delays due to transistor gate length. In addition, reduce d interconnect line cross sections translate into increased current de nsities for logic devices, Line failure due to electromigration become s a serious concern for aluminum/copper interconnect lines with cross sections significantly below those used in state-of-the-art semiconduc tor devices. Many semiconductor manufacturers envision switching to lo wer-resistance, electromigration-stable copper conductors and lower pe rmittivity (low-k) organic dielectrics. This revolutionary path is com plicated by the absence of manufacturable processes and integration kn owledge for copper and low-k dielectrics. Evolutionary process enhance ments will thus drive current materials as far as possible until the a dvantages of new materials outweigh their risks. This article discusse s alternative interconnect structures for future generation devices. I t will point out where fundamental limitations will likely demand new process and material sets, and where the advantages of new materials a nd processes may compel their use.