DESIGN OF CMOS CHECKERS WITH IMPROVED TESTABILITY OF BRIDGING AND TRANSISTOR STUCK-ON FAULTS

This work presents a design technique for CMOS static and dynamic chec kers (to be used in self-checking circuits), that allows the detection of all internal single transistor stuck-on and bridging faults causin g unacceptable degradations of the circuit dynamic performance (but no t logical errors). Such a technique exploits simple voltage detector c ircuits to make sure that the intermediate faulty voltages inevitably produced by the faults of interest are always propagated at the checke r output as logic errors. With the use of our technique, the main disa dvantages of static: checkers, so far preventing their use in practica l applications, are overcome. The method has been applied to the parti cular case of two-rail (static as well as dynamic) checkers and its va lidity has been verified by means of electrical level simulations.