STRUCTURE AND TECHNIQUE FOR PSEUDORANDOM-BASED TESTING OF SEQUENTIAL-CIRCUITS

Presented is a register structure and generator design which enables n on-scan sequential testing using parallel pseudorandom-based patterns applied to the circuit's primary inputs. The proposed register structu re and register control strategy uses the circuit under test's (CUT's) natural sequential activity to periodically alter a register's output bias to a value near 0.5 (i.e. alter the spread of 1's in the output stream). Thus, over time, it is possible to introduce a larger spread circuit states than that normally reachable when parallel pseudorandom -based test patterns are applied to the input lines of a CUT. Using th e register modification, a Simple hardware generation system can be de signed and is suitable for both on-chip and external testing. Experime nts indicate that high fault coverage is attainable in a relatively sh ort test time.