SEMI-DETERMINISTIC FAULT-INDEPENDENT TEST-GENERATION AND ITS IMPACT ON ATPG PERFORMANCE

A new semi-deterministic fault-independent test generation (SDTG) meth od suitable for phase I of automatic test pattern generation (ATPG) sy stems is introduced. The new method combines the advantages of random test generation (RTG), parallel pattern, single fault propagation, and maximizes the number of detected faults in phase I by deriving test v ectors from those already simulated. The new method has been implement ed in an ATPG system to assess its performance. Experimental results o btained from the ISCAS85 benchmark circuits show that the fault covera ge achieved in phase I by the proposed SDTG method is higher than that obtained by using RTG. The total test generation time for several of the benchmark circuits improved by up to 17% while achieving the same overall fault coverage. The extra time spent in phase I by the new SDT G method is more than repaid by the reduction in time needed in phase II, and therefore reduces the total test generation time for most circ uits.