FAST VLSI-EFFICIENT SELF-ROUTING PERMUTATION NETWORK

Authors
CAM H FORTES JAB
Citation
H. Cam et Jab. Fortes, FAST VLSI-EFFICIENT SELF-ROUTING PERMUTATION NETWORK, I.E.E.E. transactions on computers, 44(3), 1995, pp. 448-453
Citations number
18
Categorie Soggetti
Computer Sciences","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture
Journal title
I.E.E.E. transactions on computers → ACNP
ISSN journal
00189340
Volume
44
Issue
3
Year of publication
1995
Pages
448 - 453
Database
ISI
SICI code
0018-9340(1995)44:3<448:FVSPN>2.0.ZU;2-Z
Abstract
A multistage self-routing permutation network is presented, This netwo rk is constructed from concentrators and digit-controlled 2 x 4 switch es. A destination tag routing scheme is used to realize any arbitrary permutation. The network has O(log(2) N) gate-delay and uses O(N-2) VL SI-area, where N is the number of inputs.(1) Assuming packet-switching is used for message transmission, the delay and VLSI-area of the netw ork are smaller than those of any self-routing permutation network pre sented to date.