REDUCED-VOLTAGE POWER PERFORMANCE OPTIMIZATION OF THE 3.6-VOLT POWERPC-601 MICROPROCESSOR

An experimental 2.0-volt low-power PowerPC 601(TM) Microprocessor buil t in a modified 3.6-volt, 0.6-mu m IBM CMOS technology is described. B y using unmodified masks from the 3.6-volt design, a 3x power savings was realized while maintaining nearly the original performance. The us e of selective scaling provides high performance at reduced power supp ly voltage. This technique, applicable to selected existing product de signs, may allow early entry into the low-power market while minimizin g new process development expense. The technique proposes hyperscaled reductions in specific electrical and physical parameters, while keepi ng horizontal layout rules unchanged. Static chip designs, which compr ise the majority of 601 circuitry, respond well to the alterations. In addition, potential reliability detractors are reduced or eliminated. Challenges to this technique include I/O interfacing and minimizing l eakages associated with low device thresholds. The 601 design and its base technology are described, along with the experimental changes. Th e paper reviews the motivation behind low-power microprocessor develop ment, alternative power-saving techniques being practiced, and opportu nities for continued power reduction.