MULTIPURPOSE DRAM ARCHITECTURE FOR OPTIMAL POWER, PERFORMANCE, AND PRODUCT FLEXIBILITY

An 18Mb DRAM has been designed in a 3.3-V, 0.5-mu m CMOS process. The array consists of four independent, self-contained 4.5Mb quadrants. Th e chip output configuration defaults to 1Mb x 18 for optimization of w afer screen tests, while 3.3-V or 5.0-V operation is selected by choos ing one of two M2 configurations. Selection of 2Mb x 9 or 1Mb x 18 ope ration with the various address options, in extended data-out or fast- page mode, is accomplished by selective wire-bonding during module bui ld. Laser fuses enable yield enhancement by substituting eight 512Kb a rray I/O slices for nine in each quadrant of the 18Mb array. This subs titution is independent in each quadrant and results in 1Mb x 16 opera tion with 2Mb x 8, 4Mb x 4, and 4Mb x 4 with any 4Mb independently sel ectable (4Mb x 4 w/4 CE). Input and control circuitry are designed suc h that performance margins are constant across output and functional c onfigurations. The architecture also provides for ''cut-downs'' to 16M b, 4.5Mb, and 4Mb chips with I/O and function as above.