Dg. Chesebro et al., OVERVIEW OF GATE LINEWIDTH CONTROL IN THE MANUFACTURE OF CMOS LOGIC CHIPS, IBM journal of research and development, 39(1-2), 1995, pp. 189-200
This paper is an overview of the methods used at the Burlington facili
ty of the IBM Microelectronics Division to improve channel-length tole
rance control in the manufacture of CMOS logic chips. We cover aspects
of 1) the impact of channel-length control on chip performance, yield
, and reliability; 2) our use of an electrical linewidth monitor which
permits high-volume, accurate measurements to quantify polysilicon ga
te linewidth variability and its improvements; and 3) our efforts to r
educe photolithographic and etching contributions to the linewidth var
iability.